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SIEMENS AG
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| Part No. |
HYB39S16160CT-7 HYB39S16160CT-5.5 HYB39S16160CT-6
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| OCR Text |
...ip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. the chip is fabricated using the infi...input and output circuits are synchronized with the positive edge of an externally supplied clock. o... |
| Description |
1M × 16-Mbit Synchronous DRAM for High-Speed Graphics Applications(16M1M × 16)同步动态RAM(用于高速图形场)
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| File Size |
111.85K /
19 Page |
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it Online |
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Cypress Semiconductor Corp.
http://
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| Part No. |
CYV15G0201DXB-BBC CYP15G0201DXB
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...nk ? technology compliant to multiple standards ? escon, dvb-asi, fibre channel and gigabit ethernet (ieee802.3z) ? cyv15g0201dxb also c...input/output clocking options multiframe? receive framer ? bit and byte alignment ? comma or full ... |
| Description |
PLENUM VGA VIDEO CABLE 100 FT -MM
Dual-channel HOTLink II Transceiver
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| File Size |
581.29K /
46 Page |
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it Online |
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Integrated Device Technology, Inc.
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| Part No. |
STAC9767XXTAEYYX STAC9766XXTAEYYX
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...84/50/52 as the pri- mary, in a multiple codec configuration conforming to the ac'97 rev. 2.3 specification . this configuration can pro- v...input frame (sdata_in) ............................................................................... |
| Description |
TWO-CHANNEL, 20-BIT, AC7 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
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| File Size |
484.24K /
97 Page |
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it Online |
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LSI Corporation
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| Part No. |
SYM53C895
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| OCR Text |
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contents v 3.3.6 memory read multiple command 3-9 3.4 con?guration registers 3-10 chapter 4 signal descriptions 4.1 voltage capabilities ...input filtering 7-9 7.5 hysteresis of scsi receiver 7-10 7.6 input current as a function of input vo... |
| Description |
PCI to Ultra2 SCSI I/O Processor with LVD（Low Voltage Differential Link）Universal Transceivers(PCIUltra2 SCSI I/O接口处理器（带低电压差分连接通用收发器）)
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| File Size |
1,172.73K /
326 Page |
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it Online |
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