|
|
![](images/bg04.gif) |
Atmel
|
Part No. |
AT93C86A
|
OCR Text |
...struction at di, the address is decoded and the data is clocked out serially on the data output pin do. the write cycle is completely self- timed and no separate erase cycle is required before write. the write cycle is only enabled when the... |
Description |
16K, 3-wire Bus Serial EEPROM (x8 or x16 organization) with Schmitt Trigger and Sequential Read.
|
File Size |
124.50K /
16 Page |
View
it Online |
Download Datasheet
|
|
|
![](images/bg04.gif) |
Atmel
|
Part No. |
AT93C56A AT93C66A
|
OCR Text |
...struction at di, the address is decoded and the data is 3-wire serial eeproms 2k (256 x 8 or 128 x 16) 4k (512 x 8 or 256 x 16) at93c56a at93c66a advance information rev. 3378e?seepr?1/04 pin configurations pin name function cs chip select... |
Description |
2K/4K, 3-wire Bus Serial EEPROM (x8 or x16 organization) with sequential read.
|
File Size |
155.40K /
18 Page |
View
it Online |
Download Datasheet
|
|
|
![](images/bg04.gif) |
SGS Thomson Microelectronics
|
Part No. |
AN1482
|
OCR Text |
...iction() is applied only to the decoded blocks that are non-null, based on the coded block pattern read from bitstream. The frame/field DCT coding is dealt with at this time: the Add_Prediction() routine can read the predictor both in frame... |
Description |
MPEG2 VIDEO DECODING ON ST100
|
File Size |
40.56K /
8 Page |
View
it Online |
Download Datasheet
|
|
|
![](images/bg04.gif) |
Cypress
|
Part No. |
PXA272
|
OCR Text |
...Considering the worst case, the decoded value of RDF should be set to 30 for extra timing margin (RDF="1111"). Subsequent read operation: Before starting a subsequent MoBL Dual-Port read, the processor should wait for at least tHZCE = 20ns ... |
Description |
Interfacing Dual Port to Intel Embedded Processor
|
File Size |
108.30K /
4 Page |
View
it Online |
Download Datasheet
|
|
|
![](images/bg04.gif) |
Intersil
|
Part No. |
HD-6409
|
OCR Text |
...icates a data sync pattern. The decoded serial NRZ data is transmitted out synchronously with the decoder clock (DCLK). SDO is forced low when RST is low. In the converter mode, SRST follows RST. In the repeater mode, when RST goes low, SRS... |
Description |
Encoder-Decoder, Manchester, 1-Mbit/s, CMOS
|
File Size |
141.44K /
12 Page |
View
it Online |
Download Datasheet
|
|
![](images/findchips_sm.gif)
Price and Availability
|