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ZARLINK[Zarlink Semiconductor Inc]
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| Part No. |
MT9046AN MT9046
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| OCR Text |
...C4, C6, C8, C16, and C19 (STS-3/oc3 clock divided by 8) output clock signals Provides 5 styles of 8 KHz framing pulses Holdover frequency ac...12 13 14 15 16 17 18 19 20 21 22 23 24
SSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32... |
| Description |
T1/E1 System Synchronizer with Holdover
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| File Size |
300.45K /
34 Page |
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PHILIPS[Philips Semiconductors]
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| Part No. |
TZA3005H TZA3005
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| OCR Text |
oc3 and STM4/OC12 transceiver
Objective specification File under Integrated Circuits, IC19 1997 Aug 05
Philips Semiconductors
Objecti...12
16
19
26
29
38, 46
34, 42
GNDTXCORE DGNDSYN
VCCD(SYN) VCCA(SYN) AGNDSYN
... |
| Description |
SDH/SONET STM1/oc3 and STM4/OC12 transceiver
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| File Size |
524.77K /
24 Page |
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it Online |
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PHILIPS[Philips Semiconductors]
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| Part No. |
TZA3012AHW
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| OCR Text |
...LOW HIGH LOW HIGH PROTOCOL STM1/oc3 STM4/OC12 STM16/OC48 STM16 + FEC GE 10GE Fibre Channel Fibre Channel BIT RATE (Mbits/s) 155.52 622.08 24...12. Limiting amplifiers The TZA3012AHW has two switchable RF line inputs. Each input has a limiting ... |
| Description |
30 Mbits/s up to 3.2 Gbits/s A-rateTM Fibre Optic Receiver
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| File Size |
234.69K /
60 Page |
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it Online |
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PHILIPS[Philips Semiconductors]
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| Part No. |
TZA3017HW
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| OCR Text |
...LOW HIGH LOW HIGH PROTOCOL STM1/oc3 STM4/OC12 STM16/OC48 STM16 + FEC GE 10GE Fibre Channel Fibre Channel BIT RATE (Mbits/s) 155.52 622.08 24...12 kHz from the carrier. If reference divider R is used, this negative value is allowed to increase ... |
| Description |
30 Mbits/s up to 3.2 Gbits/s A-rate fibre optic transmitter
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| File Size |
213.48K /
52 Page |
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it Online |
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ZARLINK[Zarlink Semiconductor Inc]
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| Part No. |
ZL30409_DDB ZL30409 ZL30409_DDA
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| OCR Text |
...C4, C6, C8, C16, and C19 (STS-3/oc3 clock divided by 8) output clock signals Provides 5 styles of 8 KHz framing pulses Holdover frequency ac...12 13 14 15 16 17 18 19 20 21 22 23 24
SSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32... |
| Description |
Dual reference frequency selectable, 3.3V Digital PLL with multiple clock outputs for T1/E1 and Stratum 4 and 4E applications, with Stratum 3 Holdover
T1/E1 System Synchronizer with Stratum 3 Holdover
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| File Size |
284.56K /
32 Page |
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it Online |
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ZARLINK[Zarlink Semiconductor Inc]
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| Part No. |
ZL30414QGC1 ZL30414 ZL30414QGC
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| OCR Text |
...-253-CORE OC-192, OC-48, OC-12, oc3 rates and ITU-T G.813 STM-64, STM-16, STM-4 and STM-1 rates. The ZL30414 accepts a CMOS compatible reference at 19.44 MHz and generates four LVPECL differential output clocks at 622.08 MHz, a CML differen... |
| Description |
SONET/SDH Clock Multiplier PLL
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| File Size |
408.73K /
24 Page |
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it Online |
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MICROCHIP
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| Part No. |
DSPIC30F6015
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| OCR Text |
.../UPDN/CN16/RD7 IC5/RD12 OC4/RD3 oc3/RD2 EMUD2/OC2/RD1
PWM2H/RE3
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PWM3L/R...12 13 14 15 16 17 18 19 20 21 22 34 35 36 37 38 39 23 24 25 26 27 28 29 30 31 32 33
60 59 58 57 5... |
| Description |
dsPIC30F Motor Control 16-bit Digital Signal Controller
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| File Size |
2,195.54K /
239 Page |
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it Online |
Download Datasheet |
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