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For bus self Found Datasheets File :: 11677    Search Time::0.812ms    
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    HYS72T128000EP-25F-B2

QIMONDA AG
Part No. HYS72T128000EP-25F-B2
OCR Text ...ity bit for address and control bus and describes its main characteristics. 1.1 features ? 240-pin pc2-6400, pc2-5300 and pc2-4200 ddr2 sd...self refresh. ? auto refresh for temperatures above 85 c t refi = 3.9 s. ? programmable self ref...
Description 128M X 72 DDR DRAM MODULE, DMA240

File Size 1,250.89K  /  64 Page

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    MB81EDS51654510

Fujitsu Component Limited.
Part No. MB81EDS51654510
OCR Text ...ble dq[63:0] * 1, * 2 i/o data bus input / output rdqs[3:0] * 2 output read data strobe wdqs[3:0] * 2 input write data strobe sa * 3 input ...self refresh mode. 3. chip select (cs ) cs enables all commands inputs, ras , cas , and we , and ad...
Description 512M Bit (4 bank x 2M word x 64 bit) Consumer Applications Specific Memory for SiP

File Size 466.82K  /  60 Page

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    CAT28C257P-12T CAT28C257P-15T

Catalyst Semiconductor
Part No. CAT28C257P-12T CAT28C257P-15T
OCR Text ...C257 is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state whe...self-timed write cycle, all I/O's will output true data during a read cycle. Toggle Bit In addition ...
Description 256K-Bit CMOS PARALLEL EEPROM

File Size 510.69K  /  12 Page

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    CY7C1231H CY7C1231H-133AXC CY7C1231H-133AXI

Cypress Semiconductor
Part No. CY7C1231H CY7C1231H-133AXC CY7C1231H-133AXI
OCR Text bus operations with zero wait states -- Data is transferred on every clock * Pin compatible and functionally equivalent to ZBTTM devices * Internally self-timed output buffer control to eliminate the need to use OE * Registered inputs for f...
Description 2-Mbit (128K x 18) Flow-Through SRAM with NoBL⑩ Architecture

File Size 438.30K  /  12 Page

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    CYPRESS[Cypress Semiconductor]
Cypress Semiconductor Corp.
Part No. CY7C1352-133AC CY7C1352-80AC CY7C1352 CY7C1352-100AC CY7C1352-143AC 7C1352
OCR Text ...MT55L256L18P * Supports 143-MHz bus operations with zero wait states -- Data is transferred on every clock * Internally self-timed output buffer control to eliminate the need to use OE * Fully registered (inputs and outputs) for pipelined o...
Description From old datasheet system
256K x18 Pipelined SRAM with NoBL Architecture(B>NoBL结构56Kx18流水线式 SRAM)

File Size 183.78K  /  12 Page

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    HYS72T512220EP-3-C2

QIMONDA AG
Part No. HYS72T512220EP-3-C2
OCR Text ...ity bit for address and control bus and describes its main characteristics. 1.1 features ? 240-pin pc2-6400 and pc2-5300 ddr2 sdram memory ...self refresh. ? auto refresh for temperatures above 85 c t refi = 3.9 s. ? programmable self ref...
Description 512M X 72 DDR DRAM MODULE, DMA240

File Size 1,586.88K  /  57 Page

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    http://
CYPRESS[Cypress Semiconductor]
Part No. CY7C1353B-66AC CY7C1353B-66BGC CY7C1353B CY7C1353B-100AC CY7C1353B-117AC CY7C1353B-40AC CY7C1353B-50AC CY7C1353B-50BGC
OCR Text ...MT55L256L18F * Supports 117-MHz bus operations with zero wait states -- Data is transferred on every clock * Internally self-timed output buffer control to eliminate the need to use OE * Registered inputs for flow-through operation * Byte W...
Description 256Kx18 Flow-Through SRAM with NoBL Architecture

File Size 447.02K  /  15 Page

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    CY7C1353G-133AXC CY7C1353G-133AXI CY7C1353G-117AXI CY7C1353G CY7C1353G-100AXC CY7C1353G-100AXI CY7C1353G-117AXC

CYPRESS[Cypress Semiconductor]
Part No. CY7C1353G-133AXC CY7C1353G-133AXI CY7C1353G-117AXI CY7C1353G CY7C1353G-100AXC CY7C1353G-100AXI CY7C1353G-117AXC
OCR Text ...es * Can support up to 133-MHz bus operations with zero wait states -- Data is transferred on every clock * Pin compatible and functionally equivalent to ZBTTM devices * Internally self-timed output buffer control to eliminate the need to ...
Description 4-Mbit (256K x 18) Flow-through SRAM with NoBL(TM) Architecture
4-Mbit (256K x 18) Flow-through SRAM with NoBL⑩ Architecture
4-Mbit (256K x 18) Flow-through SRAM with NoBL Architecture

File Size 213.28K  /  13 Page

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