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  holdover Datasheet PDF File

For holdover Found Datasheets File :: 681    Search Time::3.859ms    
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    ZL3040706

Zarlink Semiconductor Inc
Part No. ZL3040706
OCR Text ..., e1, e3, stm-1 and 19.44 mhz ? holdover accuracy of 4x10 -12 meets gr-1244 stratum 3e and itu-t g.812 requirements ? continuously monitors both references for frequency accuracy exceeding 12 ppm ? provides ?hit-less? reference switchin...
Description SONET/SDH Network Element PLL

File Size 594.49K  /  57 Page

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    ACS8522BT

Semtech Corporation
Part No. ACS8522BT
OCR Text ...e supports free-run, locked and holdover modes, with mode selection controlled automatically by an internal state machine, or forced by register configuration. the acs8522bt accepts up to four independent input sec reference clock sour...
Description orderSynchronous Equipment Timing Source for Stratum 3/4E/4, SMC and Ethernet Systems

File Size 1,580.99K  /  122 Page

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    ZL30402_QCC ZL30402QCC1 ZL30402

ZARLINK[Zarlink Semiconductor Inc]
Part No. ZL30402_QCC ZL30402QCC1 ZL30402
OCR Text ...E1, E2, E3, STM-1 and 19.44 MHz holdover accuracy to 1x10 meets GR-1244 Stratum 3E and ITU-T G.812 requirements Continuously monitors Primary and Secondary reference clocks Provides "hit-less" reference switching Compensates for Master Cloc...
Description SONET/SDH Network Element PLL

File Size 384.78K  /  41 Page

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    M602-012.8M

Connor-Winfield Corporation
Part No. M602-012.8M
OCR Text ... designs 0.28ppm with stratum 3 holdover, 0.5 1 0 485 pad connection 1 voltage control or n/c 2 do not connect 3 do not connect 4 ground 5 output 6 do not connect 7 do not connect 8 supply, vcc ordering information 2 type: precision tcxo ...
Description Precision Sub-Miniature 5.0x3.2mm TCXO / VCTCXO

File Size 183.51K  /  4 Page

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    574

CTS Corporation
Part No. 574
OCR Text ...y, 0.280 ppm max ? stratum 3 holdover per gr-1244 ? +3.3 or +5 vdc operation ? operating temperature to 0c to +70c ? output enable standard ? electrical frequency adjustment option ? tape & reel packaging ? rohs complia...
Description Stratum 3 TCXO/TCVCXO

File Size 191.65K  /  5 Page

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    STC4130 STC4130-I

List of Unclassifed Manufacturers
Part No. STC4130 STC4130-I
OCR Text ... switches ? better than 0.1 ppb holdover accuracy ? programmable bandwidth, from 90mhz to 107hz, for both t0 and t4 dpll ? supports spi or parallel bus interface ? ieee 1149.1 jtag boundary scan ? available in tq100 rohs package t0_master...
Description Synchronous Clock for SETS

File Size 422.85K  /  44 Page

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    ZL5001806 ZL50018GAC ZL50018QCC

Zarlink Semiconductor Inc
Zarlink Semiconductor I...
Part No. ZL5001806 ZL50018GAC ZL50018QCC
OCR Text ...544 mhz output) ? dpll provides holdover, freerun and jitter attenuation features with four independent reference source inputs ? programmable key dpll parameters (filter corner frequency, locking range, auto-holdover hysteresis range, ...
Description 2 K Digital Switch with Enhanced Stratum 3 DPLL

File Size 996.96K  /  136 Page

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    AD9557 AD9557/PCBZ AD9557BCPZ AD9557BCPZ-REEL7

Analog Devices
Part No. AD9557 AD9557/PCBZ AD9557BCPZ AD9557BCPZ-REEL7
OCR Text ... gr-1244 stratum 3 stability in holdover mode supports smooth reference switchover with virtually no disturbance on output phase supports telcordia gr-253 jitter generation, transfer, and tolerance for sonet/sdh up to oc-192 systems s...
Description Dual Input Multiservice

File Size 1,161.00K  /  92 Page

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    Zarlink Semiconductor, Inc.
Part No. ZL30105QDG1
OCR Text ...nd a 2 khz multi-frame pulse ? holdover frequency accuracy of 1x10 -8 ? selectable loop filter 1.8 hz, 3.6 hz or 922 hz ? less than 24 ps rms intrinsic jitter on the 19.44 mhz output clock, compliant with gr-253-core oc-3 and g.813 stm-...
Description T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110 SPECIALTY TELECOM CIRCUIT, PQFP64

File Size 1,096.74K  /  52 Page

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    82V3391BEQGBLANK

Integrated Device Technology
Part No. 82V3391BEQGBLANK
OCR Text ...upports 1.1x10 -5 ppm absolute holdover accuracy and 4.4x10 -8 ppm instantaneous holdover accuracy ? supports hitless reference switch ing to minimize phase transients on t0 dpll output to be no more than 0.61 ns ? supports programmable in...
Description SYNCHRONOUS ETHERNET WAN PLL and Clock Generation for IEEE-1588

File Size 56.37K  /  5 Page

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For holdover Found Datasheets File :: 681    Search Time::3.859ms    
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