...bines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is con...flop on the LOW-to-HIGH transition of CLKAB. When OEAB is LOW, the outputs are active. When OEAB is ...
Description
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
...e A-data is stored in the latch/flip-flop. When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latch/flip-flop. To ensure the hig...
Description
18-bit registered driver with inverted register enable 3-State
...e A-data is stored in the latch/flip-flop. When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latch/flip-flop. To ensure the hig...
...e A-data is stored in the latch/flip-flop. When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latch/flip-flop. To ensure the hig...
Description
20-bit registered driver with inverted register enable 3-State
flip-flop
April 1988 Revised July 1999
74F112 Dual JK Negative Edge-Triggered flip-flop
General Description
The 74F112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state changes are...
...ation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of th...flop outputs terminal count output positive supply voltage
74HC/HCT160
Fig.1 Pin configuration...
Description
Presettable synchronous BCD decade counter asynchronous reset CAP 2700UF 6.3V ELECT FC RADIAL HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16 74HC/HCT160; Presettable synchronous BCD decade counter; asynchronous reset
...ation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of th...flop outputs terminal count output positive supply voltage
74HC/HCT161
Fig.1 Pin configuration...
...ation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of th...flop outputs terminal count output positive supply voltage
74HC/HCT162
Fig.1 Pin configuration...
...ation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of th...flop outputs terminal count output positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logi...