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IDT
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| Part No. |
MPC940L
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| OCR Text |
... capability to select either a differential lvpecl or an lvcmos compatible input. th e 18 outputs are 2.5 v or 3.3 v lvcmos compatible and feature the drive strength to drive 50 ? series or parallel terminated transmission lines. wit... |
| Description |
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
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| File Size |
1,092.46K /
11 Page |
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it Online |
Download Datasheet
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Alliance Semiconductor ...
ALSC[Alliance Semiconductor Corporation]
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| Part No. |
ASM4SSTVF32852 ASM4SSTVF32852-114BT ASM4ISSTVF32852-114BR ASM4ISSTVF32852-114BT ASM4SSTVF32852-114BR
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| OCR Text |
Differential clock signals. Supports SSTL_2 class II specifications on inputs and outputs. Low voltage operation. VDD = 2.3V to 2.7V.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB m... |
| Description |
DDR 24-Bit to 48-Bit Registered Buffer
SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA114
Specialty Clock Management
2.3 V -2.7 V, DDR 24-bit to 48-bit registered buffer
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| File Size |
106.12K /
13 Page |
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it Online |
Download Datasheet |
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IDT
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| Part No. |
IDT74SSTVF16857
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| OCR Text |
...ass I style data inputs/outputs Differential CLK input RESET control compatible with LVCMOS levels Flow-through architecture for optimum PCB design Drive up to equivalent of 14 SDRAM loads Latch-up performance exceeds 100mA ESD >2000V per M... |
| Description |
14-BIT REGISTERED BUFFER
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| File Size |
52.11K /
6 Page |
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it Online |
Download Datasheet |
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IDT
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| Part No. |
IDT74SSTVF16859
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| OCR Text |
...ass I style data inputs/outputs Differential CLK input RESET control compatible with LVCMOS levels Latch-up performance exceeds 100mA ESD >2...to 26-bit registered buffer designed for 2.3V-2.7V VDD for PC1600 - PC2700 and 2.5V-2.7V VDD for PC3... |
| Description |
13-BIT TO 26-BIT REGISTERED BUFFER
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| File Size |
62.52K /
7 Page |
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it Online |
Download Datasheet |
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Price and Availability
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